Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 17
UG074 (v2.2) February 22, 2010
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Chapter 2
Ethernet MAC Architecture
This chapter describes the architecture of the Virtex®-4 FPGA Embedded Tri-Mode
Ethernet Media Access Controller (MAC). It contains the following sections:
• “Architecture Overview”
• “Ethernet MAC Primitive”
• “Ethernet MAC Signal Descriptions”
Architecture Overview
The Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC supports 10/100/1000 Mb/s data
rates and is designed to IEEE Std 802.3-2002 specifications. The Ethernet MAC can operate
as a single speed Ethernet MAC at 10, 100, or 1000 Mb/s or as a tri-mode Ethernet MAC.
The Ethernet MAC supports the IEEE standard GMII and the RGMII protocols to reduce
the width of the bus to the external physical interface. A 1000BASE-X PCS/PMA sublayer,
when used in conjunction with the Virtex-4 FPGA RocketIO™ Multi-Gigabit Transceiver
(MGT), provides a complete on-chip 1000BASE-X implementation.
Figure 2-1 shows a block diagram of the Ethernet MAC block. The block contains two
Ethernet MACs sharing a single host interface. The host interface can use either the generic
host bus or the DCR bus through the DCR bridge. Each Ethernet MAC has an address filter
to accept or reject incoming frames on the receive datapath. The Ethernet MAC outputs
raw statistic vectors to enable statistics gathering. The statistics vectors are multiplexed to
reduce the number of pins at the block boundary. An external module (StatsIP0 and/or
StatsIP1) can be designed and implemented in the FPGA fabric to accumulate all the
statistics of the Ethernet MAC. The “Interfacing to an FPGA Fabric-Based Statistics Block”
section provides additional information on the statistics block.
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English