Xilinx Virtex-4 User Manual

80 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 3: Client, Host, and MDIO Interfaces
R
Figure 3-41 shows the read timing from the configuration registers. The words are similar,
but the upper HOSTOPCODE bit = 1. The contents of the register appear on
HOSTRDDATA[31:0] the HOSTCLK edge after the register address is asserted onto
HOSTADDR. HOSTMIIMSEL acts as a read enable. It must be held Low for an even
number of clock cycles during a read operation.
Address Filter Registers
Address Filter Register access includes the address filter registers and the multicast
address table registers. The Ethernet MAC has five address filter registers with access
through the host interface (Table 3-15).
Figure 3-41: Configuration Register Read Timing
HOSTCLK
HOSTADDR[8:0]
HOSTADDR[9]
HOSTOPCODE[1]
HOSTMIIMSEL
HOSTRDDATA[31:0]
ug074_3_43_080805
Table 3-15: Address Filter Register
Address Register Description
0x380 Unicast Address (Word 0)
0x384 Unicast Address (Word 1)
0x388 Multicast Address Table Access (Word 0)
0x38C Multicast Address Table Access (Word 1)
0x390 Address Filter Mode
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English