Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 123
UG074 (v2.2) February 22, 2010
10/100/1000 Serial Gigabit Media Independent Interface (SGMII)
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10/100/1000 Serial Gigabit Media Independent Interface (SGMII)
The SGMII physical interface was defined by Cisco Systems. The data signals operate at a
rate of 1.25 Gb/s, and the sideband clock signals operate at 625 MHz. Due to the speed of
these signals, differential pairs are used to provide signal integrity and minimize noise.
The sideband clock signals are not implemented in the Ethernet MAC. Instead, the MGT is
used to transmit and receive data with clock data recovery (CDR).
When using SGMII mode, the MGT must be instantiated in the design to connect with the
Ethernet MAC. For more information on SGMII, refer to the Serial GMII specification v1.7.
This interface only supports full-duplex operation.
SGMII RX Elastic Buffer
The RX elastic buffer can be implemented in one of two ways:
• Using the buffer present in the MGTs
• Using a larger buffer that is implemented in the FPGA logic
This section describes the selection and implementation of two options in the following
subsections:
• “Using the MGT RX Elastic Buffer”
• “Using the FPGA Logic Elastic Buffer”
RX Elastic Buffer Implementations
Selecting the Buffer Implementation from the GUI
The GUI for the Ethernet MAC provides two alternative options under the heading
“SGMII Capabilities.” These options are:
1. 10/100/1000 Mb/s (clock tolerance compliant with Ethernet specification).
Default setting; provides the implementation using the RX elastic buffer in FPGA
fabric. This alternative RX elastic buffer utilizes a single block RAM to create a buffer
twice as large as the one present in the RocketIO™ transceivers, subsequently
consuming extra logic resources. However, this default mode provides reliable SGMII
operation under all conditions.
2. 10/100/1000 Mb/s (restricted tolerance for clocks) OR 100/1000 Mb/s.
Uses the RX elastic buffer present in the RocketIO transceivers. This is half the size and
can potentially under- or overflow during SGMII frame reception at 10 Mb/s
operation. However, there are logical implementations where this can be proven
reliable; if so, it is favored because of its lower logic utilization.
Option 1, the default mode, provides the implementation using the RX elastic buffer in the
FPGA logic. This alternative RX elastic buffer utilizes a single block RAM to create a buffer
that is twice as large as the one present in the MGT, therefore consuming extra logic
resources. However, this default mode provides reliable SGMII operation.
Option 2 uses the RX elastic buffer in the MGTs. This buffer, which is half the size of the
buffer in Option 1, can potentially underflow or overflow during SGMII frame reception at
10 Mb/s operation (see “The FPGA RX Elastic Buffer Requirement”). However, in logical
implementations where this case is proven reliable, this option is preferred because of its
lower logic utilization.
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English