Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 131
UG074 (v2.2) February 22, 2010
10/100/1000 Serial Gigabit Media Independent Interface (SGMII)
R
10/100/1000 SGMII Clock Management
Figure 4-24 shows the clock management used with the SGMII interface. At a line rate of
1.25 Gb/s or below, oversampling is used by the built-in MGT digital receiver to recover
clock and data. Chapter 3 of UG076
, Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide
provides more details about the digital receiver oversampling operation. The inputs of the
GT11CLK_MGT primitive connect to an external, high-quality reference clock with a
frequency of 250 MHz specifically for the MGT. The output SYNCLK1OUT connects to the
PLL reference clock input REFCLK1. TXOUTCLK1 is derived from the transmitter PLL.
TXOUTCLK1 feeds TXUSRCLK2 and the PHYEMAC#GTXCLK. RXRECCLK1 feeds a
BUFR that is used to clock the internal elastic buffer. This buffer is only necessary for
SGMII. The output of the BUFR also drives RXUSRCLK2. RXUSRCLK and TXUSRCLK are
both tied to ground.
Figure 4-24: SGMII Clock Management
UG074_3_61_070607
BUFR
GT11
FPGA Fabric RX Elastic
Buffer
GT11CLK_MGT
MGTCLKP
MGTCLKN
SYNCLK1OUT
REFCLK1
RXUSRCLK2
RXRECCLK1
RXUSRCLK‘0’
250 MHz
BUFG
TXUSRCLK2
TXOUTCLK1
TXUSRCLK‘0’
EMAC#
PHYEMAC#GTXCLK
CLIENTEMAC#TXCLIENTCLKIN
EMAC#CLIENTTXCLIENTCLKOUT
CLIENTEMAC#RXCLIENTCLKIN
EMAC#CLIENTRXCLIENTCLKOUT
Client
Logic
BUFG
X
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English