Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 93
UG074 (v2.2) February 22, 2010
MDIO Interface
R
MDIO Interface
Introduction to MDIO
The MDIO interface for 1 Gb/s operation (and slower speeds) is defined in IEEE Std 802.3,
Clause 22. This two-wire interface consists of a clock (MDC) and a shared serial data line
(MDIO).
An MDIO bus in a system consists of a single Station Management (STA) master
management entity and a number of MDIO Managed Device (MMD) slave entities.
Figure 3-46 illustrates a typical system. All transactions, read or write, are initiated by the
STA entity. All MMD devices, if addressed, must respond to the transactions from the STA.
The two different MDIO transaction types for writes and reads are described in “Write
Transaction,” and “Read Transaction.”
These abbreviations are used in this chapter:
Figure 3-46: Typical MDIO-Managed System
OP Operation code
PHYAD PHY address
PRE Preamble
REGAD Register address
ST Start of frame
TA Turnaround
MAC 1 MAC 2
STA
MDC
MDIO
MMD
MMD
MMD
MMD
MMD
MMD
UG074_3_71_112705
www.BDTIC.com/XILINX

Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English