Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 37
UG074 (v2.2) February 22, 2010
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Chapter 3
Client, Host, and MDIO Interfaces
This chapter provides useful design information for user interaction with the Virtex®-4
FPGA Tri-Mode Ethernet MAC. It contains the following sections:
• “Client Interface,” page 37
• “Host Interface,” page 72
• “MDIO Interface,” page 93
Client Interface
The client interface is designed for maximum flexibility for matching the client switching
fabric or network processor interface.
Both the transmit and receive data pathway can be configured to be either 8 bits wide or
16 bits wide, with each pathway synchronous to the CLIENTEMAC#TXCLIENTCLKIN
(transmit) or CLIENTEMAC#RXCLIENTCLKIN (receive) for completely independent
full-duplex operation.
Figure 3-1 shows a block diagram of the transmit client interface. In 16-bit client mode,
PHYEMAC#MIITXCLK functions as CLIENTEMAC#TXCLIENTCLKIN/2.
TIEEMAC#CONFIGVEC[66] selects between an 8-bit or 16-bit client interface.
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English