Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 13
UG074 (v2.2) February 22, 2010
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Preface
About This Guide
This document is the Virtex®-4 FPGA Embedded Tri-Mode Ethernet MAC User Guide.
Guide Contents
This user guide contains the following chapters:
• Chapter 1, “Introduction,” introduces the Virtex-4 FPGA Embedded Tri-Mode
Ethernet MAC and summarizes its features.
• Chapter 2, “Ethernet MAC Architecture,” describes the architecture of the Ethernet
MAC and defines its signals.
• Chapter 3, “Client, Host, and MDIO Interfaces,” provides design information for the
client, host, and MDIO interfaces.
• Chapter 4, “Physical Interface,” describes design considerations for the supported
interfaces when using the Ethernet MAC.
• Chapter 5, “Miscellaneous Functions,” provides useful information for designing
with the Ethernet MAC.
• Chapter 6, “Use Models,” describes some available models and how to interface the
Ethernet MAC to a processor DCR or an FPGA statistics block.
• Chapter 7, “Using the Embedded Ethernet MAC,” describes the Verilog and VHDL
CORE Generator™ wrappers.
• Appendix A, “Ethernet MAC Timing Model,” provides details on the timing
parameters of the Ethernet MAC timing model.
Additional Resources
For additional information, go to http://www.xilinx.com/support.