Xilinx Virtex-4 User Manual

34 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 2: Ethernet MAC Architecture
R
RocketIO Multi-Gigabit Transceiver Signals
Table 2-15 shows the signals used to connect the Ethernet MAC to the RocketIO Multi-
Gigabit Transceiver (see UG076
, Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide).
PHYEMAC#RXDV Input
10/100 MII
The data valid control signal from the PHY.
GMII
RGMII The RGMII_RX_CTL_RISING signal.
SGMII
The RXREALIGN signal from the MGT.
1000BASE-X
PHYEMAC#RXER Input
10/100 MII
The error control signal from the PHY.
GMII
RGMII
The RGMII_RX_CTL_FALLING signal from the
PHY.
PHYEMAC#RXD[7:0] Input
10/100 MII
PHYEMAC#RXD [3:0] is the received data signal
from the PHY. PHYEMAC#RXD [7:4] is left
unconnected.
GMII The received data signal to the PHY.
RGMII
PHYEMAC#RXD [3:0] is the
RGMII_RXD_RISING and PHYEMAC#RXD
[7:4] is the RGMII_RXD_FALLING signal from
the PHY.
SGMII
The RX_DATA from the MGT.
1000BASE-X
PHYEMAC#COL Input
10/100 MII
The collision control signal from the PHY, used
in half-duplex mode.
SGMII
The TXRUNDISP signal from the MGT.
1000BASE-X
PHYEMAC#CRS Input 10/100 MII
The carrier sense control signal from the PHY,
used in half-duplex mode.
Table 2-14: PHY Data and Control Signals (Cont’d)
Signal Direction Mode Description
Table 2-15: Multi-Gigabit Transceiver Connections
Signal Direction Description
EMAC#PHYENCOMMAALIGN Output Enable RocketIO PMA layer to realign to commas.
EMAC#PHYLOOPBACKMSB Output Loopback tests within the RocketIO Multi-Gigabit Transceivers.
EMAC#PHYMGTRXRESET Output Reset to RocketIO RXRESET.
EMAC#PHYMGTTXRESET Output Reset to RocketIO TXRESET.
EMAC#PHYPOWERDOWN Output Power-down the RocketIO Multi-Gigabit Transceivers.
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English