Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 163
UG074 (v2.2) February 22, 2010
Interfacing to an FPGA Fabric-Based Statistics Block
R
When the Ethernet MAC Is Implemented with the DCR Bus
When the Ethernet MAC is implemented with the DCR bus connected directly to the
PPC405, the host bus signals of the Ethernet MAC can access the statistics counters.
The host bus I/O signals of the Ethernet MAC are enabled for statistics counter access
when a DCR read operation is made for address codes 0x000 to 0x02F and 0x040 to
0x04F inclusive (Table 3-30, page 91 describes the DCR address code space). This use of
the host bus I/O signals provides a means of accessing the FPGA fabric from the processor
with space for 64 addresses.
When the DCR bus is instructed to access registers in this address code region, the DCR
bridge translates the DCR commands into generic host read signals on the host bus I/O
signals. The DCR transaction is encoded on the host bus signals HOSTRDDATA[31:0] and
HOSTMIIMRDY as described in Table 6-2 and Figure 6-2. These signals can access
statistics counters in the same way as if a standalone host bus is used. The statistics values
read from statistics counters are captured from the host bus signals HOSTWRDATA[31:0]
as shown in Figure 6-2. The data read from the host bus can then be accessed by reading
the DCR data registers.
Table 6-2: DCR to Host Mapping
EMAC Host Bus Port
Port Direction on
EMAC
DCR Register
Equivalent Standalone Host
Bus Signal
HOSTRDDATA
[15] Out
HOSTREQ
[14:13] Out
HOSTOPCODE[1:0]
[10] Out
cntlReg[21],
EMAC1Sel
HOSTEMAC1SEL
[9:0] Out
cntlReg[22:31],
Address Code
HOSTADDR[9:0]
HOSTMIIMRDY Out
HOSTMIIMSEL
HOSTWRDATA[31:0] In
dataRegLSW /
dataRegMSW
HOSRTRDDATA[31:0]
HOSTMIIMSEL In
HOSTMIIMRDY
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English