Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 167
UG074 (v2.2) February 22, 2010
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Chapter 7
Using the Embedded Ethernet MAC
This chapter describes how the embedded Ethernet MAC can be incorporated into a
design using the CORE Generator™ tool.
Accessing the Ethernet MAC from the CORE Generator tool
Generating the Virtex®-4 FPGA embedded Ethernet MAC wrapper files using the CORE
Generator tool greatly simplifies the use of the Virtex-4 FPGA Ethernet MAC. The Ethernet
MAC is highly configurable, and not all pins/interfaces are required for every
configuration. The CORE Generator tool allows the configuration of the Ethernet MAC to
be selected using a GUI and generates HDL wrapper files for the configuration. These
wrapper files hide much of the complexity of the Ethernet MAC by bringing out only the
interface signals for the selected configuration. Accessing the Ethernet MAC from the
CORE Generator tool provides the following features:
• Allows selection of one or both of the two Ethernet MACs (EMAC0 and EMAC1) from
the embedded Ethernet MAC primitive
• Sets the values of the EMAC0 and EMAC1 attributes based on user options
• Provides user-configurable Ethernet MAC physical interfaces
• Supports MII, GMII, RGMII v1.3, RGMII v2.0, SGMII, and 1000BASE-X
PCS/PMA interfaces
• Provides off-chip connections for physical interfaces by instantiating RocketIO™
transceivers, and logic as required, for the selected physical interfaces
• Provides an optimized clocking scheme for the selected physical interface and
instantiates the required clock buffers, DCMs, and other required components.
• Provides a simple FIFO-loopback example design, which is connected to the MAC
client interfaces
• Provides a simple demonstration test bench based on the selected configuration
• Generates VHDL or Verilog wrapper files
Simulating the Ethernet MAC using the Ethernet MAC wrappers
The Ethernet MAC wrappers generated by the CORE Generator tool also provide a
loopback design of the embedded Ethernet MAC, a demo test bench to exercise the
wrappers and the example design, and scripts for simulation and implementation.
The example design and the demo testbench are set up to provide fast simulation cycles
(for configurations using DCMs). To speed up simulations that require DCMs, the DCM
reset signals by default are not connected to the 200 ms reset pulse that is required by
Virtex-4 devices (see UG070,
Virtex-4 FPGA User Guide). To use the design in hardware, a
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English