Xilinx Virtex-4 User Manual

134 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 4: Physical Interface
R
Management Registers
SGMII has a similar PCS sublayer managed register block defined in IEEE Std 802.3-2002
Clause 37. This set of 10 management registers, accessed through MDIO, is described in the
1000BASE-X PCS/PMA section (“Management Registers,” page 140). However, the auto-
negotiation Advertisement Register (register 4) and the auto-negotiation Link Partner
Ability BASE Register (register 5) are different in the SGMII specification. Table 4-7 and
Table 4-8 describe these two registers with regard to the SGMII specification.
Table 4-7: SGMII Auto-Negotiation Advertisement Register (Register 4)
Bit(s) Name Description Attributes Default Value
4.15:0
All bits SGMII defined value sent from the MAC
to the PHY.
Read Only 000000000000001
Table 4-8: SGMII Auto-Negotiation Link Partner Ability Base Register (Register 5)
Bit(s) Name Description Attributes Default Value
5.15 Link up/down
1 = Link up.
0 = Link down.
Read only 1
5.14 Acknowledge
Used by the auto-negotiation function to
indicate reception of a link partner’s
base or next page.
Read only 0
5.13 Reserved Always return 0.Returns 00
5.12 Duplex mode
1 = Full Duplex.
0 = Half Duplex.
Read only 00
5.11:10 Speed
00 = 10 Mb/s.
01 = 100 Mb/s.
10 = 1000 Mb/s.
11 = Reserved.
Read only 00
5.9:1 Reserved Always returns 0s. Returns 0s 000000000
5.0 Reserved Always returns 1.Returns 11
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English