Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 169
UG074 (v2.2) February 22, 2010
R
Appendix A
Ethernet MAC Timing Model
This appendix explains the timing parameters associated with the Ethernet MAC block. It
is intended to be used in conjunction with the Timing Analyzer (TRCE) report from
Xilinx® software.
Many signals enter and exit the Ethernet MAC block (as shown in Figure 2-3, page 21). The
model presented in this appendix treats the Ethernet MAC block as a “black box.”
Propagation delays internal to the Ethernet MAC block logic are ignored. Signals are
characterized with setup and hold times for inputs, and with clock to valid output times
for outputs.
There are seven clocks associated with the Ethernet MAC block. Table 2-4, page 25 briefly
describes the clock signals necessary to drive the Virtex®-4 FPGA Embedded Tri-Mode
Ethernet MAC.
Timing Parameters
Parameter designations are constructed to reflect the functions they perform as well as the
I/O signals to which they are synchronous. The following subsections explain the meaning
of each of the basic timing parameter designations used in Table A-1 through Table A-6.
Input Setup/Hold Times Relative to Clock
Basic Format:
ParameterName_SIGNAL
where
ParameterName = T with subscript string defining the timing relationship
SIGNAL = name of Ethernet MAC signal synchronous to the clock
ParameterName Format:
T
MACxCK
= Setup time before clock edge
T
MACCKx
= Hold time after clock edge
where:
x = {C (Control inputs)} {D (Data inputs)}
Setup/Hold Time (Examples):
T
MACDCK_TXD
/T
MACCKD_TXD
setup/hold times of TX data input relative to the rising
edge of CLIENTEMAC#RXCLIENTCLKIN
www.BDTIC.com/XILINX

Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English