Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 65
UG074 (v2.2) February 22, 2010
Client Interface
R
Operation
Figure 3-31 illustrates the FIFO occupancy over time.
1. The average FIFO occupancy of the left Ethernet MAC gradually increases over time
due to the clock tolerances. At point A, the occupancy has reached the threshold of 7/8
occupancy, triggering the maximum duration pause control frame request.
2. Upon receiving the pause control frame, the right Ethernet MAC ceases transmission.
3. After the right Ethernet MAC ceases transmission, the occupancy of the FIFO attached
to the left Ethernet MAC rapidly empties. The occupancy falls to the second threshold
of 3/4 occupancy at point B, triggering the zero duration pause control frame request
(the pause cancel command).
4. Upon receiving this second pause control frame, the right hand Ethernet MAC
resumes transmission.
5. Normal operation resumes, and the FIFO occupancy again gradually increases over
time. At point C, the flow control cycle repeats.
Statistics Vector
Transmitter Statistics Vector
TX_STATISTICS_VECTOR contains the statistics for the frame transmitted. The vector is
driven synchronously by the transmitter clock, CLIENTEMAC#TXCLIENTCLKIN,
following frame transmission. The bit field definition for the transmitter statistics vector is
defined in Table 3-4.
Figure 3-31: Flow Control Implementation Triggered from FIFO Occupancy
Time
FIFO Occupancy
3/4
7/8
5/8
1/2
Full
A
B
C
ug074_3_33a_052005
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English