Xilinx Virtex-4 User Manual

74 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 3: Client, Host, and MDIO Interfaces
R
Host Clock Frequency
The host clock (HOSTCLK) is used to derive the MDIO clock, MDC, and is subject to the
same frequency restrictions. See the Virtex-4 FPGA Data Sheet
for the HOSTCLK frequency
parameters.
Configuration Registers
The Ethernet MAC has seven configuration registers. These registers are accessed through
the host interface and can be written to at any time. Both the receiver and transmitter logic
only respond to configuration changes during IFGs. The configurable resets are the only
exception, because the reset is immediate.
Configuration of the Ethernet MAC is performed through a register bank accessed through
the Host interface. Any time an address shown in Table 3-7 is accessed, a 32-bit read or
write is performed from the same configuration word, with the exception of the read-only
Ethernet MAC mode configuration register and the RGMII/SGMII configuration register.
Only the speed selection is both readable and writable in the Ethernet MAC mode
configuration register.
The configuration registers and the contents of the registers are shown in Table 3-8 through
Table 3-14.
Table 3-6: Management Interface Transaction Types
Transaction HOSTMIIMSEL HOSTADDR[9]
Configuration/Address Filter 01
MDIO access 1X
Table 3-7: Configuration Registers
{HOSTEMAC1SEL, HOST_ADDR[9:0]} Register Description
0x200 Receiver Configuration (Word 0)
0x240 Receiver Configuration (Word 1)
0x280 Transmitter Configuration
0x2C0 Flow Control Configuration
0x300 Ethernet MAC Mode Configuration
0x320 RGMII/SGMII Configuration
0x340 Management Configuration
Notes:
1. HOSTEMAC1SEL acts as bit 10 of HOSTADDR.
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English