Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 27
UG074 (v2.2) February 22, 2010
Ethernet MAC Signal Descriptions
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DCR Bus Interface Signals
Table 2-6 outlines the DCR bus interface signals.
Reset and CLIENTEMAC#DCMLOCKED Signals
Table 2-7 describes the Reset signal.
Table 2-8 describes the CLIENTEMAC#DCMLOCKED signal.
Table 2-6: DCR Bus Signals
Signal Direction Description
DCREMACCLK Input Clock for the DCR interface from the PowerPC processor.
DCREMACABUS[8:9] Input
Two LSBs of the DCR address bus. Bits[0] through [7] are decoded
in conjunction with the PowerPC block.
DCREMACREAD Input DCR read request.
DCREMACWRITE Input DCR write request.
DCREMACDBUS[0:31] Input DCR write data bus.
DCREMACENABLE
(1)
Input
When using the DCR bus, this signal is connected directly to the
PPC405 output port DCREMACENABLER for DCR bus access.
When using the host bus interface, the signal is connected to the
logic ground.
EMACDCRDBUS[0:31] Output DCR read data bus.
EMACDCRACK Output DCR acknowledge.
DCRHOSTDONEIR
(1)
Output
Interrupt signal to the PowerPC processor when the Ethernet
MAC register access is done.
Notes:
1. All the DCR bus signals are internally connected to the PowerPC processor except for the DCREMACENABLE and
DCRHOSTDONEIR signals.
Table 2-7: Reset Signal
Signal Direction Description
Reset Input Asynchronous reset of both Ethernet MACs.
Table 2-8: CLIENTEMAC#DCMLOCKED Signal
Signal Direction Description
CLIENTEMAC#DCMLOCKED Input
If a DCM is used to derive any of the clock signals, the LOCKED
port of the DCM must be connected to the
CLIENTEMAC#DCMLOCKED port. The Ethernet MAC is held
in reset until CLIENTEMAC#DCMLOCKED is asserted High.
If a DCM is not used, both CLIENTEMAC#DCMLOCKED ports
from EMAC0 and EMAC1 must be tied High.
If any Ethernet MAC is not used, CLIENTEMAC#DCMLOCKED
must be tied to High.
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English