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Performance Tests
PDH Binary Interfaces (Option UH3, [US7])
Description
This test verifies that the PDH Binary Interface External Clock input meets its
specification. The Clock input, Clock output, Data input and Data output are verified
during self test.
Equipment Required
Procedure
External Clock Thresholds
1. Recall the HP 37717C DEFAULT SETTINGS as shown on 3-2.
2. Connect up the equipment as shown in Figure 3-55.
Rate (Option
UKK [USB]
Unstructured
PDH)
700 kb/s to 50 Mb/s (TTL)
700 kb/s to 170 Mb/s (ECL)
Rate (Option
UKJ [USA]
Structured
PDH
2.048 Mb/s ± 10% (ECL & TTL)
8.448 Mb/s ± 10% (ECL & TTL)
34.368 Mb/s ± 10% (ECL & TTL)
139.264 Mb/s ± 10% (ECL only)
Format Nominal squarewave, 60/40 to 40/60 duty cycle
Logic
Threshold
1.5V (TTL), -1.3V (ECL), ground, signal mean level
Termination Nominal TTL into 75Ω to ground;
Nominal ECL into 75Ω to -2V
Digital Transmission Analyzer : HP 3764A Option 006
Signal Generator : HP 8657B
Oscilloscope : HP 54503A
75Ω/50Ω Matching Pad : HP 11825B
ECL Termination : HP 10086A
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