Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
7-8
7.3.2.2 System Management Interrupt During HALT Cycle
Since SMI# is an asynchronous signal, it may be generated at any time. A condition of interest
arises when an SMI# occurs while the CPU is in a HALT state. To give the system designer max-
imum flexibility, the processor allows an SMI# to optionally exit the HALT state. Figure 7-3
shows that the CPU normally re-executes the HALT instruction after RSM; however, by modify-
ing the HALT restart slot in the SMM State Dump area, the SMM handler can redirect the instruc-
tion pointer past the HALT instruction.
Figure 7-3. SMI# During HALT
A2508-01
State
Save
SMI#
SMM
Handler
Instr
HALT
State
Resume
Instr Instr
#1 #2
#3 #4
Halted State
Option
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