Intel 386 User Manual

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
18-2
• Place all device output pins into their inactive drive (high-impedance) state, allowing
external hardware to drive connections that the processor normally drives
The test-logic unit (Figure 18-1) is fully compliant with IEEE Standard 1149.1. It consists of the
test access port (TAP), the test access port controller, the instruction register (IR), and three data
registers (IDCODE, BYPASS, and BOUND). It also includes logic for generating necessary
clock and control signals.
Figure 18-1. Test Logic Unit Connections
A2340-01
IR Register
TAP
Controller
IDCODE Register
BYPASS Register
BOUND Register
TRST#
TDO
TCK
TDI
Output
Stage
. . . . . .
TMS


Intel 386 Specifications

General

Architecture	x86
Clock Speed	12 MHz to 40 MHz
Transistor Count	275, 000
Data Bus Width	32-bit
Address Bus Width	32-bit
Instruction Set	x86
Introduced	1985
Maximum Memory	4 GB
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
MMU	Yes
Voltage	5V
Model	Intel 386
Package	PGA
Process	1.5 μm to 1 μm