iv Table of Contents
Performance Verification
5.1 Introduction 5-1
5.1.1 List of Tested Characteristics 5-1
5.1.2 Calibration Cycle 5-1
5.2 Test Equipment Required 5-2
5.2.1 Test Records 5-2
5.3 Turn On 5-2
5.4 Input Impedance 5-3
5.4.1 Channel Input Impedance 5-3
5.4.2 External Trigger Input Impedance 5-7
5.5 Leakage Current 5-9
5.5.1 Channel Leakage Current 5-9
5.5.2 External Trigger Leakage Current 5-12
5.6 Peak-Peak Noise Level 5-14
5.7 DC Accuracy 5-16
5.7.1 Positive DC Accuracy 5-16
5.7.2 Negative DC Accuracy 5-19
5.8 Offset Accuracy 5-20
5.8.1 Positive Offset Accuracy 5-20
5.8.2 Negative Offset Accuracy 5-22
5.9 Bandwidth 5-23
5.9.1 Description 5-23
5.10 Trigger Level 5-28
5.10.1 Description 5-28
5.10.2 Channel Trigger at 0 Division Threshold 5-28
5.10.3 Channel Trigger at +2.5 Divisions Threshold 5-31
5.10.4 Channel Trigger at −2.5 Divisions Threshold 5-32
5.11 Time Base Accuracy 5-34
5.11.1 Description 5-34
5.11.2 Clock Verification Procedure 5-34
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