Xilinx 7 Series User Manual

100 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 3: Transmitter
Using TX Buffer Bypass in Multi-Lane Mode
This section describes the steps required to perform the multi-lane TX buffer bypass alignment
procedure.
• Master: In a multi-lane application, the buffer bypass master is the lane that is the source of
TXOUTCLK.
• Slave: All the lanes that share the same TXUSRCLK/TXUSRCLK2, which is generated from
the TXOUTCLK of the buffer bypass master.
X-Ref Target - Figure 3-13
Figure 3-13: TX Phase Alignment to Minimize TX Lane-to-Lane Skew
GTP TX
Lane 0
Skew
Before TX Phase Alignment After TX Phase Alignment
Reduced Skew
Parallel clocks
are independent
Parallel clocks are
phase aligned to the
same clock edge
GTP TX
Lane 0
GTP TX
Lane 1
GTP TX
Lane 1
UG482_c3_114_020413
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Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600