Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 45
UG482 (v1.9) December 19, 2016
Reset and Initialization
GTP Transceiver TX Component Reset
TX PMA and TX PCS can be reset individually. GTTXRESET must be driven constantly Low
during the TXPMARESET or TXPCSRESET process before finish.
Driving TXPMARESET from High to Low starts the PMA reset process. TXPCSRESET must be
driven constantly Low during the TXPMARESET process. In sequential mode (Figure 2-16), the
reset state machine automatically starts the PCS reset after finishing the PMA reset, if
TXUSERRDY is High.
Driving TXPCSRESET from High to Low starts the PCS reset process when TXUSERRDY is
High. TXPMARESET must be driven constantly Low when the PCS is in reset process. In
sequential mode, the reset state machine only resets the PCS (see Figure 2-17).
X-Ref Target - Figure 2-15
Figure 2-15: GTP Transceiver Transmitter Reset after GTTXRESET Pulse
GTTXRESET
TXUSERRDY
TXRESETDONE
TX RESET FSM IDLE IDLEWAIT TXPMARESET TXPCSRESET
TXPMARESET_TIME TXPCSRESET_TIME
UG482_c2_115_020713
X-Ref Target - Figure 2-16
Figure 2-16: TXPMARESET in Sequential Mode
X-Ref Target - Figure 2-17
Figure 2-17: TXPCSRESET in Sequential Mode
TXPMARESET
TXUSERRDY
TXRESETDONE
TX RESET FSM IDLE IDLEWAIT TXPMARESET TXPCSRESET
TXPMARESET_TIME TXPCSRESET_TIME
UG482_c2_116_020713
TXPCSRESET
TXUSERRDY
TXRESETDONE
TX RESET FSM IDLE IDLEWAIT TXPCSRESET
TXPCSRESET_TIME
UG482_c2_116_020713
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Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English