Xilinx 7 Series User Manual

62 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 2: Shared Features
Table 2-24 defines the power-down attributes.
TXPD[1:0] In TXUSRCLK2
(TXPDELECIDLEMODE
makes this port
asynchronous)
Powers down the TX lane
according to the PCI Express
PIPE protocol encoding.
00: P0 (normal operation)
01: P0s (low recovery time
power down)
10: P1 (longer recovery time;
Receiver Detection still on)
11: P2 (lowest power state)
Attributes can control the
transition times between these
power-down states.
TXPDELECIDLEMODE In Async Determines if TXELECIDLE and
TXPD should be treated as
synchronous or asynchronous
signals.
TXPHDLYPD In Async TX phase and delay alignment
circuit power down. It is set to
1'b0 in TX buffer bypass mode.
0: Power up the TX phase and
delay alignment circuit.
1: Power down the TX phase
and delay alignment circuit.
RXPHDLYPD In Async RX phase and delay alignment
circuit power down. It is set to
1'b0 in RX buffer bypass mode.
0: Power up the RX phase and
delay alignment circuit.
1: Power down the RX phase
and delay alignment circuit.
Table 2-24: Power-Down Attributes
Attribute Type Description
PD_TRANS_TIME_FROM_P2 12-bit Hex Counter settings for programmable
transition time from P2 state for PCIe. The
recommended value from the 7 Series
FPGAs Transceivers Wizard should be
used.
PD_TRANS_TIME_NONE_P2 8-bit Hex Counter settings for programmable
transition time to/from all states except P2
for PCIe. The recommended value from the
7 Series FPGAs Transceivers Wizard
should be used.
Table 2-23: Power-Down Ports (Cont’d)
Port Dir Clock Domain Description
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Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English