Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 85
UG482 (v1.9) December 19, 2016
TX 8B/10B Encoder
Ports and Attributes
Table 3-7 lists the ports required by the TX 8B/10B encoder.
Note:
There are no TX encoder attributes.
Table 3-7: TX 8B/10B Encoder Ports
Port Dir
Clock
Domain
Description
TX8B10BBYPASS[3:0] In TXUSRCLK2 This active-High port allows byte-interleaved data to bypass 8B/10B on
a per-byte basis. TX8B10BEN must be High to use this per-byte bypass
mode.
TX8B10BBYPASS [3] corresponds to TXDATA[31:24]
TX8B10BBYPASS [2] corresponds to TXDATA[23:16]
TX8B10BBYPASS [1] corresponds to TXDATA[15:8]
TX8B10BBYPASS [0] corresponds to TXDATA[7:0]
TX8B10BBYPASS[x] = 1, encoder for byte x is bypassed.
TX8B10BBYPASS[x] = 0, encoder for byte x is used.
TX8B10BEN In TXUSRCLK2 TX8B10BEN is set High to enable the 8B/10B encoder.
TX_DATA_WIDTH must be set to 20 or 40 when the 8B/10B encoder is
enabled.
0: 8B/10B encoder bypassed. This option reduces latency.
1: 8B/10B encoder enabled.
TXCHARDISPMODE[3:0] In TXUSRCLK2 Set High to work with TXCHARDISPVAL to force running disparity
negative or positive when encoding TXDATA. Set Low to use normal
running disparity. Refer to Table 3-6 for a detailed definition.
TXCHARDISPMODE[3] corresponds to TXDATA[31:24]
TXCHARDISPMODE[2] corresponds to TXDATA[23:16]
TXCHARDISPMODE[1] corresponds to TXDATA[15:8]
TXCHARDISPMODE[0] corresponds to TXDATA[7:0]
TXCHARDISPVAL[3:0] In TXUSRCLK2 Work with TXCHARDISPMODE to provide running disparity control.
Refer to Table 3-6 for detailed information.
TXCHARDISPVAL[3] corresponds to TXDATA[31:24]
TXCHARDISPVAL[2] corresponds to TXDATA[23:16]
TXCHARDISPVAL[1] corresponds to TXDATA[15:8]
TXCHARDISPVAL[0] corresponds to TXDATA[7:0]
TXCHARISK[3:0] In TXUSRCLK2 When High, indicates the corresponding data byte on TXDATA is a valid
K character.
TXCHARISK[3] corresponds to TXDATA[31:24]
TXCHARISK[2] corresponds to TXDATA[23:16]
TXCHARISK[1] corresponds to TXDATA[15:8]
TXCHARISK[0] corresponds to TXDATA[7:0]
A TXCHARISK bit should be driven Low when the corresponding
data byte from TXDATA is set to bypass the 8B/10B encoder.
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Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English