Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 139
UG074 (v2.2) February 22, 2010
1000BASE-X PCS/PMA
R
16-Bit Data Client
Figure 4-28 shows the clock management used with the 1000BASE-X PCS/PMA interface
and a 16-bit data client. This mode supports 1.25 Gb/s and 2.5 Gb/s line rates. For a
2.5 Gb/s line rate, clock and data are recovered from the incoming data stream.
The inputs of the GT11CLK_MGT primitive connect to an external, high-quality reference
clock with a frequency of 250 MHz for 1.25 Gb/s and 2.5 Gb/s line rates. The output
SYNCLK1OUT connects to the PLL reference clock input REFCLK1. TXOUTCLK1,
Figure 4-28: 1000BASE-X PCS/PMA (16-Bit Data Client) Clock Management
UG074_3_64_012408
GT11
GT11CLK_MGT
MGTCLKP
MGTCLKN
SYNCLK1OUT
REFCLK1
RXUSRCLK2
RXUSRCLK‘0’
250 MHz
BUFG
TXUSRCLK2
TXOUTCLK1
RXLOCK
TXLOCK
TXUSRCLK‘0’
Ethernet MAC
DCM
User
Application
BUFG
BUFG
X
CLIENTEMAC#TXCLIENTCLKIN
EMAC#CLIENTTXCLIENTCLKOUT
CLIENTEMAC#RXCLIENTCLKIN
EMAC#CLIENTRXCLIENTCLKOUT
PHYEMAC#GTXCLK
EMAC#CLIENTTXCMIIMIICLKOUT
CLIENTEMAC#TXGMIIMIICLKIN
CLIENTEMAC#DCMLOCKED
PHYEMAC#MIITXCLK
PHYEMAC#RXCLK
CLKFB
CLKIN
CLK0
Locked
CLKDV
RESET
X
BUFG
www.BDTIC.com/XILINX

Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English