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Xilinx Virtex-4 User Manual

Xilinx Virtex-4
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Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010
02/07/06 1.4 In Chapter 2, “Ethernet MAC Architecture”:
Added EMAC#CLIENTRXCLIENTCLKOUT to Table 2-2, page 19.
In Chapter 5, “Miscellaneous Functions”:
•Corrected “Client RX Data/Control Interface,” page 55.
Inserted new text to “Length/Type Field Error Checks,” page 52, “Tri-Mode RGMII v2.0,”
page 115, and “10/100/1000 SGMII Clock Management,” page 121.
Edited waveforms in Figure 3-39, page 66.
Added sections to Table 3-36, page 88.
•Added “Introduction to MDIO,” page 90, “MDIO Implementation in the EMAC,” page 92,
“Tri-Mode Operation with Byte PHY Enabled (Full-Duplex Only),” page 109, and
“1000BASE-X PCS/PMA (8-bit Data Client) Clock Management,” page 126.
Added IDELAY component to Figure 3-61, Figure 3-62, Figure 3-63, and Figure 3-64.
Revised the GT11 block in Figure 3-72 and Figure 3-73. Modified text in “10/100/1000
SGMII Clock Management,” page 121, “8-Bit Data Client,” page 129, and “16-Bit Data
Client,” page 130.
In Chapter 6, “Use Models”:
•Replaced “Interfacing to an FPGA Fabric-Based Statistics Block,” page 154 with new
content.
Revised example code in “Writing to the PHY Registers Using MDIO,” page 153.
In Chapter 7, “Ethernet MAC Wrappers”:
Added new text to “VHDL and Verilog CORE Generator Wrappers,” page 159.
•Added “Advanced Clocking,” page 155 and “Client Side Data Width,” page 157 options.
•Replaced “File Generation” with new content.
•Replaced Figure 5-1, page 153.
02/09/06 1.4.1 Cleaned up formatting issues. No content changes.
Date Version Revision
www.BDTIC.com/XILINX

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Xilinx Virtex-4 Specifications

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BrandXilinx
ModelVirtex-4
CategoryMotherboard
LanguageEnglish

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