Xilinx Virtex-4 User Manual

UG074 (v2.2) February 22, 2010 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
11/11/06 1.5 • Book restructuring of Chapter 3 content:
•
Sections on Host, Client, and MDIO interfaces remain in Chapter 3, now called “Client, Host,
and MDIO Interfaces.”
• Pulled out section on Physical Interface to new Chapter 4, “Physical Interface.”
• Pulled out sections on Clock Frequency Support, Ethernet MAC Configuration, and Auto-
Negotiation Interrupt to new Chapter 5, “Miscellaneous Functions.”
• Globally changed all instances of PHYEMAC#TXD to EMAC#PHYTXD.
•Section “Features” in Chapter 1: Added full-duplex qualifier for SGMII support.
• Table 3-30: Added EMAC1 registers IRSTATUS, IRENABLE, MIIMWRDATA, and
MIIMCNTL.
• Updated/corrected Figure 3-48, Figure 4-1, Figure 4-3, Figure 4-22, and Figure 4-24.
•Section “SGMII RX Elastic Buffer” added to Chapter 4, “Physical Interface.”
• Corrected section “1 Gb/s RGMII Clock Management” in Chapter 4.
•Section “10/100/1000 SGMII Clock Management” in Chapter 4: The external, high-quality
reference clock for the RocketIO transceiver changed from 125 MHz to 250 MHz. The GT11
clock schemes are simplified as shown in Figure 4-24.
•Section “1000BASE-X PCS/PMA (8-bit Data Client) Clock Management” in Chapter 4: The
GT11 clock schemes are simplified as shown in Figure 4-27.
•Section “1000BASE-X PCS/PMA Clock Management” in Chapter 4: The external, high-
quality reference clock for the 16-bit Data Client MGT changed from 125 MHz to 250 MHz.
The GT11 clock schemes are simplified as shown in Figure 4-28.
• Table 4-13: Corrected 4.8:7 Pause, 10 and 11 (reversed)
•Section “MGT Elastic Buffer (Ring Buffer)” in Chapter 4: Corrected underflow/overflow
marks, and as a result corrected maximum frame size (Table 4-4).
•Section “Transmit Clocking Scheme” in Chapter 5: Corrected description of inputs used to
generate client-side clock.
•Section “Reading the PHY Registers Using MDIO” in Chapter 6: Corrected decode address.
•Section “Writing to the PHY Registers Using MDIO” in Chapter 6: Corrected register
address for EMAC1 Management Configuration; corrected decode address.
• Chapter 7, “Using the Embedded Ethernet MAC” updated.
03/27/07 1.6 • Table 2-9: Removed Note (1).
• Table 2-11: Revised Note (1).
• Table 3-5: Removed exception from description of Length/Type Out of Range.
• Table 3-20: Corrected default value for bit 31 (Promiscuous Mode Enable).
• Chapter 4: Multiple revisions in block schematic diagram figures.
• Chapter 4: Former section “1000BASE-X PCS/PMA (8-bit Data Client) Clock Management”
in Chapter 4 incorporated into
section “8-Bit Data Client.”
• Table 4-3: Consolidated “RISING” and “FALLING” RGMII signals into single signals with
revised descriptions. Added Note (1) to RGMII_TX_CTL_# and RGMII_RX_CTL_#.
Date Version Revision
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English