Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010
08/20/07 1.7 • Replaced screen shots with updated images from v4.5 software.
• Table 2-11: Revised description of TIEEMAC#CONFIGVEC[63].
•Section “Length/Type Field Error Checks” in Chapter 3: Numerous textual revisions
throughout this section.
•Section “Receiving a PAUSE Control Frame” in Chapter 3: Last paragraph revised.
• Table 3-9: Revised definition of Receiver Configuration register bit [25] (LT_DIS).
• Figure 4-7 through Figure 4-10 and Figure 4-12 through Figure 4-16 and accompanying
text: Added IDELAY element to clock input.
• Figure 4-24: Corrected placement of BUFG to TXCLIENTCLKOUT.
• Made other typographical edits.
02/06/08 1.8 • Added conditions causing assertion of EMAC#CLIENTRXBADFRAME to “Frame
Reception with Errors,” page 53.
• Rewrote description of ALIGNMENT_ERROR bit in Table 3-5, page 70.
• Updated Figure 4-28, page 139.
•Added “Core Latency” in Appendix A.
08/13/08 1.9 • Corrected transposition error in the description column for bit [1] in Table 3-13, page 78
(values 0 and 1 were switched in second sentence).
• Corrected transposition error in the description column for bits 5.8:7 in Table 4-14, page 144
(values 01 and 10 were switched).
• Rewrote item number 1 for 1000BASE-X auto-negotiation summary (“Overview of
Operation,” page 151).
• Updated the link in the first bullet of “Global Buffer Usage,” page 165.
05/12/09 2.0 • Chapter 4:
In sections “1 Gb/s GMII Only,” page 107, “Tri-Mode Operation,” page 109, “Tri-
Mode Operation with Byte PHY Enabled (Full-Duplex Only),” page 110, “1 Gb/s
RGMII Clock Management,” page 115, “Tri-Mode RGMII v2.0,” page 117, and “Tri-
Mode RGMII v1.3,” page 120, changed the description of the method used to delay
the received clock (GMII_RX_CLK in case of GMII and RGMII_RXC in case of
RGMII) with respect to data. Original method described use of IDELAY and BUFG.
Revised method describes use of a DCM and BUFG.
In Figure 4-7, page 107, Figure 4-8, page 108, Figure 4-9, page 110, Figure 4-10,
page 111, Figure 4-12, page 115, Figure 4-13, page 116, Figure 4-14, page 118,
Figure 4-15, page 119, Figure 4-16, page 121, and “16-Bit Data Client,” page 139,
Replaced IDELAY block in clock path with DCM.
• Chapter 6:
“Simulation Models,” page 155: Removed description of SmartModels. Replaced
references to SmartModel with references to SecureIP throughout this section. Added
“SecureIP Model,” page 155.
• Chapter 7:
Removed content discussing Ethernet MAC wrappers and replaced it with“Using the
Embedded Ethernet MAC,” page 167.
Date Version Revision
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English