Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 105
UG482 (v1.9) December 19, 2016
TX Pattern Generator
Table 3-21 defines the pattern generator attribute.
Use Models
The pattern generation and check function are usually used for verifying link quality tests and also
for jitter tolerance tests. For link quality testing, the test pattern is chosen by setting TXPRBSSEL
and RXPRBSSEL to a non-000 value, and RXPRBS_ERR_LOOPBACK is set to 0 (Figure 3-18).
Only the PRBS pattern is recognized by the RX pattern checker.
Table 3-20: Pattern Generator Ports
Port Name Dir Clock Domain Description
TXPRBSSEL[2:0] In TXUSRCLK2 Transmitter PRBS generator test pattern
control.
000: Standard operation mode (test pattern
generation is off)
001: PRBS-7
010: PRBS-15
011: PRBS-23
100: PRBS-31
101: PCI Express compliance pattern.
Only works with 20-bit and 40-bit modes
110: Square wave with 2 UI (alternating
0s/1s)
111: Square wave with 16 UI or 20 UI
period (based on data width)
TXPRBSFORCEERR In TXUSRCLK2 When this port is driven High, errors are
forced in the PRBS transmitter. While this
port is asserted, the output data pattern
contains errors. When TXPRBSSEL is set to
000, this port does not affect TXDATA.
Table 3-21: Pattern Generator Attribute
Attribute Type Description
RXPRBS_ERR_LOOPBACK 1-bit Binary When set to 1, causes RXPRBSERR bit to be
internally looped back to TXPRBSFORCEERR
of the same GTP transceiver. This allows
synchronous and asynchronous jitter tolerance
testing without worrying about data clock domain
crossing.
When set to 0, TXPRBSFORCEERR forces onto
the TX PRBS.
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Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English