142 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 4: Receiver
Ports and Attributes
Table 4-11 defines the CDR ports.
Table 4-11: CDR Ports
Port Dir Clock Domain Description
RXCDRFREQRESET In Async Reserved. Tied Low.
RXCDRHOLD In Async Hold the CDR control loop frozen.
RXCDROVRDEN In Async Reserved.
RXCDRRESET In Async Reserved. Tied Low.
RXCDRRESETRSV In Async Reserved.
RXRATE[2:0] In RXUSRCLK2
(RXRATEMODE
makes this port
asynchronous)
This port dynamically controls the setting for the
RX serial clock divider D (see Table 4-16) and it
is used with RXOUT_DIV attribute.
3'b000: Use RXOUT_DIV divider value
3'b001: Set D divider to 1
3'b010: Set D divider to 2
3'b011: Set D divider to 4
3'b100: Set D divider to 8
RXBUF_RESET_ON_RATE_CHANGE
attribute enable optional automatic reset.
RXCDRLOCK Out Async Reserved.
RXOSHOLD In Async When set to 1'b1, the current value of the offset
cancellation is held.
When set to 1'b0, the offset cancellation is
adapted.
RXOSOVRDEN In Async When set to 1'b1, the Offset Cancellation is
controlled by the RX_OS_CFG attribute.
When set to 1'b0, the AGC is controlled by the
RXOSHOLD signal.
RXOSCALRESET In Async Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used.
RXOSINTPD In Async Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used.
RXOSINTCFG[3:0] In Async Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used..
RXOSINTD0[3:0] In Async Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used.
RXOSINTOVRDEN In Async Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used.
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