Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 143
UG482 (v1.9) December 19, 2016
RX CDR
Table 4-12 defines the CDR related attributes.
RXOSINTSTROBE In Async Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used.
RXOSINTHOLD In Async Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used.
RXOSINTTESTOVRDEN In Async Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used.
RXOSINTSTARTED Out Async Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used.
RXOSINTSTROBESTARTED Out Async Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used.
RXOSINTDONE Out Async Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used.
Table 4-11: CDR Ports (Cont’d)
Port Dir Clock Domain Description
Table 4-12: CDR Attributes
Attribute Type Description
CFOK_CFG 43-bit Binary Reserved. The recommended value from
the 7 Series FPGAs Transceivers Wizard
should be used.
CFOK_CFG2 7-bit Binary Reserved. The recommended value from
the 7 Series FPGAs Transceivers Wizard
should be used.
CFOK_CFG3 7-bit Binary Reserved. The recommended value from
the 7 Series FPGAs Transceivers Wizard
should be used.
RXCDR_CFG 83-bit Hex CDR configuration. The recommended
value from the 7 Series FPGAs
Transceivers Wizard should be used.
RXCDR_LOCK_CFG 6-bit Binary CDR Lock loop configuration. The
recommended value from the 7 Series
FPGAs Transceivers Wizard should be
used.
RXCDR_HOLD_DURING_EIDLE Binary Enables the CDR to hold its internal states
during an optional PCI Express reset
sequence during electrical idle.
RXCDR_FR_RESET_ON_EIDLE Binary Enables automatic reset of the CDR
frequency during the optional PCI Express
reset sequence during electrical idle.
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Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English