Xilinx VCK190 Series User Manual

• Part number: MT53D512M32D2DS-046 WT:D (dual die LPDDR4 SRAM)
• Component descripon
○ 16 Gb (512 Mb x 32)
○ 1.1V 200-ball WFBGA
○ DDR4-2133
The VCK190 XCVC1902 ACAP PL DDR interface performance is documented in the Versal Prime
Series Data Sheet: DC and AC Switching Characteriscs (DS956). The VCK190 board LPDDR4
component memory interfaces adhere to the constraints guidelines documented in the PCB
guidelines for DDR4 secon of Versal ACAP PCB Design User Guide (UG863). The VCK190 DDR4
component interface is a 40Ω impedance implementaon. Other memory interface details are
also available in the Versal ACAP Memory Resources Architecture Manual (AM007). For more
memory component details, see the Micron MT53D512M32D2DS data sheet at the Micron
website. The detailed ACAP connecons for the feature described in this secon are
documented in the VCK190 board XDC le, referenced in Appendix B: Xilinx Design Constraints.
System Reset POR_B
[Figure 3, callout 35]
POR_B is the Versal ACAP processor reset, which can be controlled by:
• SYSCTLR (U125)
• PC4 header (J36)
• MIO EBM (external boot module on J212)
• FTDI USB JTAG chip (U20)
In the following gure, U235 allows direconal open drain level shiing for all of these masters,
and J326 allows them to be bused together if desired. The h channel buers POR_B out to
the EBM (external boot module) as DC_PS_POR_B. The TPS389001 U10 supervisor chip holds
POR_B o unl power is valid. The VCK190 board POR circuit is shown in the gure.
Chapter 3: Board Component Descriptions
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 27
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Xilinx VCK190 Series Specifications

General

Brand	Xilinx
Model	VCK190 Series
Category	Motherboard
Language	English