Xilinx VCK190 Series User Manual

A secure digital (SD) card connector is provided for boong and le system storage. This
interface is used for the SD boot mode and supports SD2.0 and SD3.0 access.
The SDIO interface signals PMC_MIO[26:36, 51] are connected to XCVC1902 ACAP bank 501,
which has its VCCO set to 3.3V. Six SD interface nets PMC_MIO[26, 29, 30:33] are passed
through a Nexperia IP4856CX25 SD 3.0-compliant voltage level-translator U104 (mounted on an
Aries adapter), present between the XCVC1902 ACAP and the SD card connector (J302). The
Nexperia IP4856CX25 U104 device provides SD3.0 capability with SDR104 performance. The
Aries adapter schemac pinout to IP4856CX25 device pinout cross-reference table is shown in
the following table and also on the VCK190 schemac page for this circuit.
The Nexperia SD3.0 level shier is mounted on an Aries adapter board (located on the boom of
the board under SD socket J302) that has the pin mapping shown in the table.
Table 8: IP4856CX25 U104 Adapter Pinout
Aries Adapter Pin Number IP4856CX25 Pin Number IP4856CX25 Pin Name
1 C1 CLK_IN
2 C3 GND
3 D3 CD
4 D2 CMD_H
5 E2 CLK_FB
6 E4 WP
7 B4 VLDO
8 C4 VSD_REF
9 A3 DIR_0
10 A4 VSUPPLY
11 B3 VCCA
12 A2 DIR_CMD
13 D1 DATA0_H
14 B2 SEL
15 B1 DATA3_H
16 E1 DATA1_H
17 E3 DIR_1_3
18 A1 DATA2_H
19 E5 DATA1_SD
20 D5 DATA0_SD
21 C5 CLK_SD
22 D4 CMD_SD
23 B5 DATA3_SD
24 A5 DATA2_SD
25 C2 ENABLE
Chapter 3: Board Component Descriptions
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 32
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Xilinx VCK190 Series Specifications

General

Brand	Xilinx
Model	VCK190 Series
Category	Motherboard
Language	English