• Programmable oscillator: Silicon Labs SI570BAB000299DG (10 MHz-945 MHz range,
200.000 MHz default)
• I2C address 0X60
• LVDS dierenal output, total stability: 61.5 ppm
Programmable HSDP SI570 Clock
[Figure 3, callout 39]
The VCK190 board has an I2C programmable SI570 low-jier 3.3V LVDS dierenal oscillator
(U5) connected to the GTY_REFCLK1 inputs of U1 GTY bank 105. The HSDP_SI570_CLK_P and
HSDP_SI570_CLK _N series capacitor coupled clock signals are connected to XCVC1902 ACAP
U1 pins J39 and J40, respecvely. At power-up, this clock defaults to an output frequency of
156.250 MHz. User applicaons or the System Controller can change the output frequency
within the range of 10 MHz to 945 MHz through the I2C bus interface. Power cycling the
VCK190 board reverts this user clock to the default frequency of 156.250 MHz.
• Programmable oscillator: Silicon Labs SI570BAB000544DG (10 MHz-945 MHz range,
156.250 MHz default)
• I2C address 0x5D
• LVDS dierenal output, total stability: 61.5 ppm
Programmable zSFP SI570 Clock
[Figure 3, callout 44]
The VCK190 board has an I2C programmable SI570 low-jier 3.3V LVDS dierenal oscillator
(U192) connected to the GTY_REFCLK0 inputs of U1 GTY bank 105. The zSFP_SI570_CLK_P
and zSFP_SI570_CLK _N series capacitor coupled clock signals are connected to XCVC1902
ACAP U1 pins L39 and L40, respecvely. At power-up, this clock defaults to an output frequency
of 156.250 MHz. User applicaons or the System Controller can change the output frequency
within the range of 10 MHz to 945 MHz through the I2C bus interface. Power cycling the
VCK190 board reverts this user clock to the default frequency of 156.250 MHz.
• Programmable oscillator: Silicon Labs SI570BAB000544DG (10 MHz-945 MHz range,
156.250 MHz default)
• I2C address 0x5D
• LVDS dierenal output, total stability: 61.5 ppm
Programmable SI570 REF Clock
[Figure 3, callout 40]
Chapter 3: Board Component Descriptions
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 47
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