Xilinx VCK190 Series User Manual

The voltage translators shown in the gure are the TXS0108E 8-bit bidireconal level shier
voltage translators for open drain and push-pull applicaons. The input voltage for the I/O to the
level translator is controlled from the VADJ, which operates in the range of 1.5V to 3.3V. With
the Versal ACAP, the I/O voltage on the XPIO (which is the primary I/O of the FMC) is a
maximum of 1.5V, so the default seng for using this FMC Pmod card is VADJ = 1.5V on the
XPIO I/O. On the output side of the level translator, this is converted to a 3.3V signal because
the Pmod specicaon is at 3.3V. 5V is also supported per the Pmod specicaon, but this
voltage is not supported without modicaon to the output power supplies of the level
translator, which are xed at 3.3V for the XM119 FMC board.
Figure 29: TXS0108E Bidirectional Voltage Level Translator
X24766-102620
Note: This level translator was specically chosen to allow bidireconal signaling at lower frequencies, such
as for I2C. The Pmod board is generic and can work with both the VCK190 and VMK180 development
kits. The pinouts are idencal between the boards, and usage should be straighorward.
Pin Mapping Pmod to FMC
The pin mapping is straighorward. The ACAP pins are connected to the input to the level
translators, which map to the output pins on the Pmod connector at 3.3V. See Figure 29 for
details.
Appendix C: Pmod FMC
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 72
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Xilinx VCK190 Series Specifications

General

Brand	Xilinx
Model	VCK190 Series
Category	Motherboard
Language	English