Xilinx VCK190 Series User Manual

• 239 ground and 17 power connecons
For more informaon about the VITA 57.4 FMC+ specicaon, see the VITA FMC Markeng
Alliance website.
FMCP1 Connector J51
[Figure 3, callout 20]
The HSPC connector J51 implements a subset of the full FMCP connecvity:
• 68 single-ended or 34 dierenal user-dened pairs (34 LA pairs: LA[00:33])
• 12 transceiver dierenal pairs
• 3 transceiver dierenal clocks
• 2 dierenal clocks
• 239 ground and 15 power connecons
FMCP2 Connector J53
[Figure 3, callout 20]
The HSPC connector J53 implements a subset of the full FMCP connecvity:
• 68 single-ended or 34 dierenal user-dened pairs (34 LA pairs: LA[00:33])
• 12 transceiver dierenal pairs
• 3 transceiver dierenal clocks
• 2 dierenal clocks
• 1 dierenal (REFCLK) clock C2M pair
• 1 dierenal (SYNC) clock C2M pair
• 239 ground and 15 power connecons
See the FPGA Mezzanine Card (FMC) VITA 57.4 specicaon for addional informaon on the
FMCP HSPC connector. The detailed ACAP connecons for the feature described in this secon
are documented in the VCK190 board XDC le, referenced in Appendix B: Xilinx Design
Constraints.
Chapter 3: Board Component Descriptions
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 59
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Xilinx VCK190 Series Specifications

General

Brand	Xilinx
Model	VCK190 Series
Category	Motherboard
Language	English