19-26
Cisco ASR 1000 Series Aggregation Services Routers SIP and SPA Software Configuration Guide
OL-14127-08
Chapter 19 Configuring the 1-Port Channelized OC-3/STM-1 SPA and 1-Port Channelized OC-12/STM-4 SPA
Verifying the Interface Configuration
LINE:
AIS = 0 RDI = 1 REI = 65 BIP(B2) = 207
Active Defects: None
Active Alarms: None
Alarm reporting enabled for: SF SLOS SLOF B1-TCA B2-TCA
BER thresholds: SF = 10e-3 SD = 10e-6
TCA thresholds: B1 = 10e-6 B2 = 10e-6
SONET/SDH Line Tables
INTERVAL CV ES SES UAS
23:15-23:20 0 0 0 0
23:00-23:15 0 0 0 0
22:45-23:00 272 1 0 5
Total of Data in Current and Previous Intervals
22:45-23:20 272 1 0 5
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SONET/SDH Path Tables
INTERVAL CV ES SES UAS
23:15-23:20 0 0 0 0
23:00-23:15 0 0 0 0
22:45-23:00 187382 2 0 0
Total of Data in Current and Previous Intervals
22:45-23:20 187382 2 0 0
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T3 1/0/0 Path 1 is up.
Hardware is SPA-1XCHSTM1/OC3
IO FPGA version: 1.7, HDLC Framer version: 0
T3/T1 Framer(1) version: 1
Sonet/SDH Framer version: 0
SUBRATE FPGA version: 1.4
HDLC controller available FIFO buffers 3760
Applique type is T3
No alarms detected.
MDL transmission is enabled
FEAC code received: No code is being received
Framing is C-BIT Parity, Cablelength is 224
Clock Source is Line
Equipment customer loopback
Data in current interval (346 seconds elapsed):
0 Line Code Violations, 0 P-bit Coding Violation
0 C-bit Coding Violation, 0 P-bit Err Secs
0 P-bit Severely Err Secs, 0 Severely Err Framing Secs
0 Unavailable Secs, 0 Line Errored Secs
0 C-bit Errored Secs, 0 C-bit Severely Errored Secs
0 Severely Errored Line Secs
0 Far-End Errored Secs, 0 Far-End Severely Errored Secs
0 CP-bit Far-end Unavailable Secs
0 Near-end path failures, 0 Far-end path failures
0 Far-end code violations, 0 FERF Defect Secs
0 AIS Defect Secs, 0 LOS Defect Secs
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CT3 1/0/0.2 is up.
Hardware is SPA-1XCHSTM1/OC3
IO FPGA version: 1.7, HDLC Framer version: 0
T3/T1 Framer(1) version: 1
Sonet/SDH Framer version: 0
SUBRATE FPGA version: 1.4
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