Figure 104: 1plc Line Sychronization Block Diagram
For Line Synchronization off and <1 PLC, reading rate increases, but measurement uncertainty and
noise increases due to the Average AC noise during the S HI phase not canceling with the S LO
phase. With line synchronization ON, the S HI and S LO measurement phases are triggered at the
rising edge of the power line zero crossing. This improves reading uncertainty and noise by >30×
while minimal reading rate reduction.
Figure 105: Line Sync Off and On <1plc