Service Request Enable Register
The Service Request Enable Register controls the generation of a service request. This register is
programmed by the user and is used to enable or disable the setting of bit B6 (RQS/MSS) by the
Status Summary Message bits (B0, B1, B2, B3, B4, B5, and B7) of the Status Byte Register. As
shown in the Status Byte Register (on page C-16) topic, a logical AND operation is performed on the
summary bits (&) with the corresponding enable bits of the Service Request Enable Register. When a
logical AND operation is performed with a set summary bit (1) and with an enabled bit (1) of the
enable register, the logic “1” output is applied to the input of the logical OR gate and, therefore, sets
the MSS/RQS bit in the Status Byte Register.
The individual bits of the Service Request Enable Register can be set or cleared by using the *SRE
common command or status.request_enable. To read the Service Request Enable Register,
use the *SRE? query or print(status.request_enable). The Service Request Enable Register
clears when power is cycled or a parameter value of 0 is sent with a status request enable command
(for example, a *SRE 0 or status.request_enable = 0 is sent). The commands to program and
read the SRQ Enable Register are listed in Status byte and service request commands (on page C-
19).
Status Byte Register
The summary messages from the status registers and queues are used to set or clear the appropriate
bits (B0, B1, B2, B3, B4, B5, and B7) of the Status Byte Register. These summary bits do not latch,
and their states (0 or 1) are dependent upon the summary messages (0 or 1). For example, if the
Standard Event Register is read, its register will clear. As a result, its summary message will reset to
0, which will then reset the ESB bit in the Status Byte Register.
The Status Byte Register also receives summary bits from itself, which sets the Master Summary
Status, or MSS, bit.
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