IEEE-488 Reference
5-12
Arm Condition Register —
This is a real-time 16-bit read-
only register that constantly updates to reflect the ORed sum-
mary of the sequence event register set. In general, if bit B1
is set, the instrument is in an arm layer. The following SCPI
query command can be used to read the Arm Condition Reg-
ister:
:STATus:OPERation:ARM:CONDition?
The Arm Condition Register and the Transition Filter are
used to set the bits of the Arm Event Register. The Transition
Filter is discussed next.
Arm Transition Filter —
The transition filter is made up of
two 16-bit registers that are programmed by the user. It is
used to specify which transition (0 to 1, or 1 to 0) of bit B1
in the Arm Condition Register will set bit B1 in the Arm
Event Register.
The filter can be programmed for positive transitions (PTR),
negative transitions (NTR) or both. When an event bit is pro-
grammed for a positive transition, the event bit in the Arm
Event Register will set when the corresponding bit in the
Arm Condition Register changes from 0 to 1. Conversely,
when programmed for a negative transition, the bit in the sta-
tus register will set when the corresponding bit in the condi-
tion register changes from 1 to 0. The transition filter
registers can be set or cleared by using the following SCPI
commands:
:STATus:OPERation:ARM:PTR <NRf>
:STATus:OPERation:ARM:NTR <NRf>
The transition filter registers can be read at any time by using
the following SCPI query commands:
:STATus:OPERation:ARM:PTR?
:STATus:OPERation:ARM:NTR?
Reading a transition filter register using the above query
commands does not affect the contents of the register.
The following operations will set (1) all the bits of the PTR
register and reset (0) all the bits of the NTR register:
1. Cycling power.
2. Sending the :STATus:PRESet command.
3. Sending the :STATus:OPERation:ARM:PTR 65535 and
:STATus:OPERation:ARM:NTR 0 commands.
Arm Event Register
— This is a latched, read-only register
whose bits are set by the Arm Condition Register and Tran-
sition Filter. Once a bit in this register is set, it will remain set
(latched) until the register is cleared by a specific clearing
operation. The bits of this register are logically ANDed with
the bits of the Arm Event Enable Register and applied to an
OR gate. The output of the OR gate is the Arm Summary Bit
that is applied to the Operation Condition Register. The fol-
lowing SCPI query command can be used to read the Arm
Event Register:
:STATus:OPERation:ARM:EVENt?
Reading this register using the above SCPI command clears
the register. The following list summarizes all operations that
will clear the Operation Event Register:
1. Cycling power.
2. Sending the *CLS common command.
3. Sending the :STATus:OPERation:ARM? query com-
mand.
Arm Event Enable Register —
This register is programmed
by the user and serves as a mask for the Arm Event Register.
When masked, a set bit (B1) in the Arm Event Register will
not set the Waiting for Arm bit in the Operation Condition
Register. Conversely, when unmasked, a set bit (b1) in the
Arm Event Register will set the Waiting for Arm bit.
Bit B1 in the Arm Event Register is masked when the corre-
sponding bit (B1) in the Arm Event Enable Register is
cleared (0). When the masked bit of the Arm Event Register
sets, it is ANDed with the corresponding cleared bit in the
Arm Event Enable Register. The logic “0” output of the AND
gate is applied to the input of the OR gate and thus, will not
set the Waiting for Arm bit in the Operation Condition Reg-
ister.
Bit B1 in the Arm Event Register is unmasked when the cor-
responding bit (B1) in the Arm Event Enable Register is set
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