IEEE-488 Reference
5-11
Reading this register using the above SCPI command does
not clear the register. The following list summarizes opera-
tions that will clear the Operation Event Enable Register:
1. Cycling power.
2. Sending the :STATus:PRESet command.
3. Sending the :STATus:OPERation:ENABle 0 command.
5.6.3 Arm event status
The reporting of the arm event is controlled by a set of 16-bit
registers; the Arm Condition Register, the Transition Filter,
Arm Event Register, and the Arm Event Enable Register.
Figure 5-8 shows how these registers are structured. Notice
in Figure 5-5 that bit B1 (In An Arm Layer) of the Arm Con-
dition Register is controlled by the sequence event register
set (see paragraph 5.6.4 for details). In general, bit B1 sets
when the instrument is in the arm layer (Arm Layer 1) or
scan layer (Arm Layer 2) of operation. An explanation of the
operation process over the bus is provided in paragraph 5.7.
The various registers used for arm event status are described
as follows: Note that these registers are controlled by the
:STATus:OPERation:ARM commands of the :STATus sub-
system (see paragraph 5.16).
Figure 5-8
Arm event status
(B14 - B2)
(B15)
(B1) (B0)
OR
Arm Event
Condition Register
Arm Event Status
Enable Register
Seq 1 = Sequence 1 (Set bit indicates that the
7002 is in an arm layer)
& = Logical AND
OR = Logical OR
PTR = Positive Transition Register
NTR = Negative Transition Register
&
&
0
Seq1
(B14 - B2)
(B15)
(B1) (B0)
0
Seq1
(B14 - B2)
(B15)
(B1) (B0)
0
Always
Zero
Seq1
PTR
NTR
Arm Event
Transition Filter
Arm Event
Status Register
(B14 - B2)(B15) (B1) (B0)
Seq1
To Waiting for Arm
Bit (Arm) of Operation
Event Condition Register
(See Figure 5-7).
From ORed
Summary of
Sequence Event
Status (See
Figure 5-9).
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