IEEE-488 Reference
5-14
Reading a transition filter register using the above query
commands does not affect the contents of the register.
The following operations will set (1) all the bits of the PTR
register and reset (0) all the bits of the NTR register:
1. Cycling power.
2. Sending the :STATus:PRESet command.
Figure 5-9
Sequence event status
(B14 - B3)
(B15) (B2)
(B1) (B0)
OR
Sequence Event
Condition Register
Service Request
Enable Register
Lay1 = Layer 1 (Set bit indicates that 7002 is
in Arm Layer 1)
Lay2 = Layer 2 (Set bit indicates that 7002 is
in Arm Layer 2)
& = Logical AND
OR = Logical OR
PTR = Positive Transition Register
NTR = Negative Transition Register
&
&
&
0
Lay2 Lay1
(B14 - B3)
(B15) (B2)
(B1) (B0)
0
Lay2 Lay1
(B14 - B3)
(B15) (B2)
(B1) (B0)
0
Always
Zero
Lay2 Lay1
PTR
NTR
Sequence Event
Transition Filter
Sequence Event
Status Register
(B14 - B3)(B15) (B2) (B1) (B0)
Lay2 Lay1
To Sequence 1 Bit
(Seq 1) of Arm
Event Condition
Register (See
Figure 5-8).
3. Sending the :STATus:OPERation:ARM:SEQuence:
PTR 65535 and :STATus:OPERation:ARM: SE-
Quence:NTR 0 commands.
Sequence Event Register —
This is a latched, read-only
register whose bits are set by the Sequence Condition Regis-
ter and Transition Filter. Once a bit in this register is set, it
will remain set (latched) until the register is cleared by a spe-
cific clearing sequence. The bits of this register are logically
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