Serial Peripheral Interface Module (SPI)
Technical Data MC68HC908AB32 — Rev. 1.0
302 Serial Peripheral Interface Module (SPI) MOTOROLA
16.13.3 SPSCK (Serial Clock)
The serial clock synchronizes data transmission between master and
slave devices. In a master MCU, the SPSCK pin is the clock output. In a
slave MCU, the SPSCK pin is the clock input. In full-duplex operation,
the master and slave MCUs exchange a byte of data in eight serial clock
cycles.
When enabled, the SPI controls data direction of the SPSCK pin
regardless of the state of the data direction register of the shared I/O
port.
16.13.4 SS
(Slave Select)
The SS
pin has various functions depending on the current state of the
SPI. For an SPI configured as a slave, the SS
is used to select a slave.
For CPHA = 0, the SS
is used to define the start of a transmission. (See
16.6 Transmission Formats.) Since it is used to indicate the start of a
transmission, the SS
must be toggled high and low between each byte
transmitted for the CPHA = 0 format. However, it can remain low
between transmissions for the CPHA = 1 format. See Figure 16-12.
Figure 16-12. CPHA/SS
Timing
When an SPI is configured as a slave, the SS
pin is always configured
as an input. It cannot be used as a general-purpose I/O regardless of the
state of the MODFEN control bit. However, the MODFEN bit can still
prevent the state of the SS
from creating a MODF error. (See 16.14.2
SPI Status and Control Register.)
NOTE:
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high-
impedance state. The slave SPI ignores all incoming SPSCK clocks,
even if it was already in the middle of a transmission.
BYTE 1 BYTE 3
MISO/MOSI
BYTE 2
MASTER SS
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
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