Motorola MC68HC908AB32 User Manual

Break Module (BRK)
Technical Data MC68HC908AB32 — Rev. 1.0
368 Break Module (BRK) MOTOROLA
22.4.1 Flag Protection During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables
software to clear status bits during the break state.
22.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and
$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
22.4.3 PIT, TIMA, and TIMB During Break Interrupts
A break interrupt stops all timer counters.
22.4.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V
TST
is present on
the RST
pin.
22.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
22.5.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine,
the user can subtract one from the return address on the stack if SBSW
is set (see Section 8. System Integration Module (SIM)). Clear the
SBSW bit by writing logic 0 to it.

Motorola MC68HC908AB32 Specifications

General

Brand	Motorola
Model	MC68HC908AB32
Category	Controller
Language	English