Input/Output (I/O) Ports
Port F
MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Input/Output (I/O) Ports 331
NOTE:
Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1. Figure 17-20 shows
the port F I/O logic.
Figure 17-20. Port F I/O Circuit
When DDRFx is a logic 1, reading address $0009 reads the PTFx data
latch. When DDRFx is a logic 0, reading address $0009 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
Table 17-7 summarizes the operation of the port F pins.
Table 17-7. Port F Pin Functions
DDRF
Bit
PTF Bit
I/O Pin
Mode
Accesses
to DDRF
Accesses to PTF
Read/Write Read Write
0X
(1)
Notes:
1. X = don’t care.
Input, Hi-Z
(2)
2. Hi-Z = high impedance.
DDRF[7:0] Pin PTF[7:0]
(3)
3. Writing affects data register, but does not affect the input.
1 X Output DDRF[7:0] PTF[7:0] PTF[7:0]
READ DDRF ($000D)
WRITE DDRF ($000D)
RESET
WRITE PTF ($0009)
READ PTF ($0009)
PTFx
DDRFx
PTFx
INTERNAL DATA BUS
PTF5 to TBCH1, PTF4 to TBCH0, PTF3 to TBCH3, PTF2 to TBCH2 of TIMB
PTF1 to TACH3, PTF0 to TACH2 of TIMA
PTFPUEx
V
DD
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