External Interrupt (IRQ)
Technical Data MC68HC908AB32 — Rev. 1.0
342 External Interrupt (IRQ) MOTOROLA
18.4.1 IRQ Pin
A logic 0 on the IRQ
pin can latch an interrupt request into the IRQ latch.
A vector fetch, software clear, or reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-
level-sensitive. With MODE set, both of the following actions must occur
to clear IRQ:
• Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic 1 to
the ACK bit in the interrupt status and control register (ISCR). The
ACK bit is useful in applications that poll the IRQ
pin and require
software to clear the IRQ latch. Writing to the ACK bit prior to
leaving an interrupt service routine can also prevent spurious
interrupts due to noise. Setting ACK does not affect subsequent
transitions on the IRQ
pin. A falling edge that occurs after writing
to the ACK bit latches another interrupt request. If the IRQ mask
bit, IMASK, is clear, the CPU loads the program counter with the
vector address at locations $FFFA and $FFFB.
• Return of the IRQ
pin to logic 1 — As long as the IRQ pin is at logic
0, IRQ remains active.
The vector fetch or software clear and the return of the IRQ pin to logic
1 may occur in any order. The interrupt request remains pending as long
as the IRQ
pin is at logic 0. A reset will clear the latch and the MODE
control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With
MODE clear, a vector fetch or software clear immediately clears the IRQ
latch.
The IRQF bit in the ISCR register can be used to check for pending
interrupts. The IRQF bit is not affected by the IMASK bit, which makes it
useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ
pin.
NOTE:
When using the level-sensitive interrupt trigger, avoid false interrupts
by masking interrupt requests in the interrupt routine.
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