RL78/G13 APPENDIX A REVISION HISTORY
R01UH0146EJ0100 Rev.1.00 1069
Sep 22, 2011
A.2 Revision History of Preceding Editions
Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition.
(1/2)
Edition Description Chapter
Change of 1.1 Features
Change of 1.6 Outline of Functions
CHAPTER 1 PIN
FUNCTIONS
Change of 2.1 (5) 128-pin products
Change of 2.1.12 80-pin products
Change of 2.1.13 100-pin products
Change of 2.1.14 128-pin products
Change of 2.1.15 Pins for each product (pins other than port pins) (6/6)
Change of caution in 2.2.5 (2) Control mode
Change of 2.2.17 VDD, EVDD0, EVDD1, VSS, EVSS0, EVSS1
Change of Type 37-C in Figure 2-1. Pin I/O Circuit List (1/2)
CHAPTER 2 PIN
FUNCTIONS
Change of Figure 3-1 to Figure 3-10
Change of description of 3.1.2 Mirror area
Change of Figure 3-11. Format of Configuration of Processor Mode Control
Register (PMC)
Change of caution in 3.1.3 Internal data memory space
Change of Figure 3-12 to Figure 3-21
Change of caution in 3.2.1 (3) Stack pointer (SP)
Change of caution in 3.2.2 General-purpose registers
CHAPTER 3 CPU
ARCHITECTURE
Modification of Table 3-1 Set Values of Internal Memory Size Switching Register
(IMS) (78K0/KB2, and 38-pin products and 44-pin products of the 78K0/KC2)
and Table 3-2 Set Values of Internal Memory Size Switching Register (IMS) and
Internal Expansion RAM Size Switching Register (IXS) (48-pin products of the
78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2)
Addition of description in 3.2.1 (2) Program status word (PSW)
Modification of Notes 2 to 4 in Table 3-8 Special Function Register List (5/5)
CHAPTER 3 CPU
ARCHITECTURE
Change of Table 4-1 (5) 128-pin products
Deletion of note and caution 3 in 4.2.5 Port 4
Change of Figure 4-56. Block Diagram of P137
Change of Table 4-7. Settings of Port Mode Register, and Output Latch When
Using Alternate Function (1/4)
CHAPTER 4 PORT
FUNCTIONS
Change of 5.1 (2) Subsystem clock
Change of Figure 5-1. Block Diagram of Clock Generator
Change of Figure 5-10. Format of Internal High-Speed Oscillator Trimming
Register (HIOTRM)
Ver.0.07
Change of Figure 5-15. CPU Clock Status Transition Diagram
CHAPTER 5 CLOCK
GENERATOR
<R>
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