Renesas RL78/G1D User Manual

RL78/G13 CHAPTER 19 RESET FUNCTION
R01UH0146EJ0100 Rev.1.00 879
Sep 22, 2011
19.1 Register for Confirming Reset Source
Many internal reset generation sources exist in the RL78/G13. The reset control flag register (RESF) is used to store
which source has generated the reset request.
The RESF register can be read by an 8-bit memory manipulation instruction.
RESET input, reset by power-on-reset (POR) circuit, and reading the RESF register clear TRAP, WDTRF, RPERF,
IAWRF, and LVIRF flags.
Figure 19-5. Format of Reset Control Flag Register (RESF)
Address: FFFA8H After reset: 00H
Note 1
R
Symbol 7 6 5 4 3 2 1 0
RESF TRAP 0 0 WDTRF 0 RPERF IAWRF LVIRF
TRAP Internal reset request by execution of illegal instruction
Note 2
0 Internal reset request is not generated, or the RESF register is cleared.
1 Internal reset request is generated.
WDTRF Internal reset request by watchdog timer (WDT)
0 Internal reset request is not generated, or the RESF register is cleared.
1 Internal reset request is generated.
RPERF Internal reset request t by RAM parity
0 Internal reset request is not generated, or the RESF register is cleared.
1 Internal reset request is generated.
IAWRF Internal reset request t by illegal-memory access
0 Internal reset request is not generated, or the RESF register is cleared.
1 Internal reset request is generated.
LVIRF Internal reset request by voltage detector (LVD)
0 Internal reset request is not generated, or the RESF register is cleared.
1 Internal reset request is generated.
Notes 1. The value after reset varies depending on the reset source.
2. The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
Cautions 1. Do not read data by a 1-bit memory manipulation instruction.
2. An instruction code fetched from RAM is not subject to parity error detection while it is being
executed. However, the data read by the instruction is subject to parity error detection.
3. Because the RL78’s CPU executes lookahead due to the pipeline operation, the CPU might read
an uninitialized RAM area that is allocated beyond the RAM used, which causes a RAM parity
error. Therefore, when enabling RAM parity error resets (RPERDIS = 1), be sure to initialize the
used RAM area + 10 bytes.

Renesas RL78/G1D Specifications

General

Brand	Renesas
Model	RL78/G1D
Category	Computer Hardware
Language	English