RL78/G13 CHAPTER 20 POWER-ON-RESET CIRCUIT
R01UH0146EJ0100 Rev.1.00 881
Sep 22, 2011
CHAPTER 20 POWER-ON-RESET CIRCUIT
20.1 Functions of Power-on-reset Circuit
The power-on-reset circuit (POR) has the following functions.
• Generates internal reset signal at power on.
The reset signal is released when the supply voltage (V
DD) exceeds 1.51 V ±0.03 V.
• Compares supply voltage (V
DD) and detection voltage (VPDR = 1.50 V ±0.03 V), generates internal reset signal when
V
DD < VPDR.
Caution If an internal reset signal is generated in the POR circuit, TRAP, WDTRF, RPERF, IAWRF, and
LVIRF flags of the reset control flag register (RESF) is cleared.
Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that
indicates the reset source is located in the reset control flag register (RESF) for when an internal reset
signal is generated by the watchdog timer (WDT), voltage-detector (LVD), illegal instruction execution,
RAM parity error, or illegal-memory access. The RESF register is not cleared to 00H and the flag is set to
1 when an internal reset signal is generated by the watchdog timer (WDT), voltage-detector (LVD), illegal
instruction execution, RAM parity error, or illegal-memory access.
For details of the RESF register, see CHAPTER 19 RESET FUNCTION.
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