Renesas RL78/G1D User Manual

RL78/G13 CHAPTER 11 A/D CONVERTER
R01UH0146EJ0100 Rev.1.00 523
Sep 22, 2011
11.7.4 Setup when using temperature sensor (example for software trigger mode and one-shot conversion mode)
Figure 11-35. Setup When Using Temperature Sensor
PER0 register setting
• ADM0 register setting
• ADM1 register setting
• ADM2 register setting
• ADUL/ADLL register setting
• ADS register setting
(The order of the settings is
irrelevant.)
The ADCEN bit of the PER0 register is set (1), and supplying the clock
starts.
• ADM0 register
FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D
conversion time.
ADMD bit: This is used to specify the select mode.
• ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the software
trigger mode.
ADSCM bit: Sequential conversion mode/one-shot conversion mode
• ADM2 register
ADREFP1, ADREFP0, and ADREFM bits: These are used to select the
reference voltage source.
ADRCK bit: This is used to select the range for the A/D conversion
result comparison value generated by the interrupt signal
from AREA1, AREA3, and AREA2.
ADTYP bit: 8-bit/10-bit resolution
• ADUL/ADLL register
These are used to specify the upper limit and lower limit A/D conversion
result comparison values.
• ADS register
ADISS and ADS4 to ADS0 bits: These are used to select temperature
sensor 0 output or internal reference
voltage output.
ADCE bit setting
The ADCE bit of the ADM0 register is set (1), and the system enters the
A/D conversion standby status.
Stabilization wait time count (1 μ s)
The software counts up to the stabilization wait time (1 μ s).
Start of A/D conversion
End of A/D conversion
The A/D conversion end interrupt (INTAD) is generated.
Note
The conversion results are stored in the ADCR and ADCRH registers.
ADCS bit setting
After counting up to the stabilization wait time ends, the ADCS bit of the
ADM0 register is set (1), and the system enters the software trigger
standby status.
Storage of conversion results in
the ADCR and ADCRH registers
End of A/D conversion
Start of setup
The A/D conversion end interrupt (INTAD) will be generated.
After ADISS is set (1), the initial conversion result cannot be used.
This is the wait time from the time when ADISS is set (1) to the time
second conversion starts.
f
Stabilization wait time (5 μ s)
Start of A/D conversion
Note Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal
being generated. In this case, the results are not stored in the ADCR, ADCRH registers.
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Renesas RL78/G1D Specifications

General

Brand	Renesas
Model	RL78/G1D
Category	Computer Hardware
Language	English