Renesas RL78/G1D User Manual

RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0146EJ0100 Rev.1.00 577
Sep 22, 2011
12.5.1 Master transmission
Master transmission is that the RL78/G13 outputs a transfer clock and transmits data to another device.
3-Wire Serial I/O CSI00 CSI01 CSI10 CSI11 CSI20 CSI21 CSI30 CSI31
Target channel Channel
0 of
SAU0
Channel
1 of
SAU0
Channel
2 of
SAU0
Channel
3 of
SAU0
Channel
0 of
SAU1
Channel
1 of
SAU1
Channel
2 of
SAU1
Channel
3 of
SAU1
Pins used SCK00,
SO00
SCK01,
SO01
SCK10,
SO10
SCK11,
SO11
SCK20,
SO20
SCK21,
SO21
SCK30,
SO30
SCK31,
SO31
INTCSI00 INTCSI01 INTCSI10 INTCSI11 INTCSI20 INTCSI21 INTCSI30 INTCSI31Interrupt
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Error detection flag None
Transfer data length 7 or 8 bits
Transfer rate Max. fCLK/2 [Hz] (CSI00), fCLK/4 [Hz] (other than CSI00)
Min. fCLK/(2 × 2
15
× 128) [Hz]
Note
fCLK: System clock frequency
Data phase Selectable by the DAPmn bit of the SCRmn register
• DAPmn = 0: Data output starts from the start of the operation of the serial clock.
• DAPmn = 1: Data output starts half a clock before the start of the serial clock operation.
Clock phase Selectable by the CKPmn bit of the SCRmn register
• CKPmn = 0: Forward
• CKPmn = 1: Reverse
Data direction MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS).
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13

Renesas RL78/G1D Specifications

General

Brand	Renesas
Model	RL78/G1D
Category	Computer Hardware
Language	English